1. Field of the Invention
This invention relates to a time base correcting apparatus in which incoming video signals are written into a memory by write clock signals modulated by time base errors and in which these written video signals are read out from the memory by read clock signals modulated by the velocity error to compensate for the time base error contained in the incoming video signals.
2. Description of the Prior Art
In general, signal recording and/or reproducing apparatus adapted for recording and/or reproducing signals by a rotary head device is subject to time base fluctuations resulting from eccentricity or irregular rotation of the rotary head or from fluctuations in the running speed of the recording medium. For high quality reproduction, it is necessary to compensate for these time base fluctuations contained in the reproduced signals. Especially, in a so-called direct FM recording type video tape recorder in which the video signals are directly frequency modulated prior to recording, residual jitters may give rise to irregular color, so that a time base correcting apparatus with an extremely high accuracy is necessitated.
For correcting the time base errors of the reproduced video signals in a VTR, a time base correcting apparatus shown for example in FIG. 1 has been used, in which the reproduced video signals are written in a memory with write clock signals modulated by the time base errors, and these written video signals are read out from the memory by the read clock signals modulated by the velocity error to correct the time base errors contained in the playback video signals.
In the conventional time base correcting apparatus shown in FIG. 1, the reproduced video signals including time base fluctuations are supplied through a signal input terminal 1 to an analog to digital converter (A/D) converter 2, while being simultaneously supplied to a sync separation circuit 3 and to a burst gate 4.
The sync separation circuit 3 separates sync signals contained in the playback or reproduced video signals to supply horizontal sync signals thereof to an AFC (automatic frequency control) circuit 5. The burst gate circuit 4 separates the burst signals contained in the incoming reproduced signals to supply the thus separated burst signals to an APC (automatic phase control) circuit 6.
In the case of a time base correcting apparatus for use with a video signal according to the NTSC system, the AFC circuit 5 generates reproducing clock pulses having a frequency equal to 910 times the horizontal sync frequency (fh), or 910 fh, that is, equal to four times the subcarrier frequency (fsc), or 4 fsc, on the basis of the horizontal sync signals supplied from the sync separating circuit 3. The thus produced reproducing clock pulses are supplied from the AFC circuit 5 to the APC circuit 6, and the AFC circuit 5 also generates write start signals Ws at an interval of a horizontal scanning period (1 H), by frequency dividing the frequency of the reproducing clock pulses by 910. The thus produced write start signals Ws are supplied to a write address generating circuit 7. The APC circuit 6 also effects phase control in such a manner as to match the phase of the reproducing clock pulse from circuit 5 with that of the burst signal supplied from the burst gate circuit 4 to form write clock signals Wck with the frequency of 910 fh which are accompanied by phase fluctuations associated with time base errors of the aforementioned incoming video signals. The write clock signals Wch are supplied from the circuit 6 to the write address generating circuit 7 and to the A/D converter 2, while the circuit 6 simultaneously forms velocity error signals having the phase of said burst signals as the reference and supplying these velocity error signals to a phase modulating circuit 9 through an analog delay circuit 8.
The phase modulating circuit 9 is supplied with reference read clock signals Rck having the frequency of 910 fh from a reference clock generator 10 and operates to phase modulate the read clock signals Rck in dependence upon the velocity error signals supplied through the analog delay circuit 8 to supply the phase-modulated read clock signals to a read address generator 11 and to a digital to analog (D/A) converter 12.
In the above described conventional time base correcting apparatus, the write clock signals Wck generated in the APC circuit 6 with the frequency of 910 fh and accompanied by phase fluctuations associated with time base errors of the incoming reproduced video signals are used for writing in a memory 13 video data that are the digitized version of the incoming video signals obtained at the A/D converter 2. The reference read clock signals Rck produced at the reference clock generator 10 with the frequency of 910 fh so as to be free from time base errors are also used for reading the video data from the memory 13. These video data are then converted in the D/A converter 12 into corresponding analog signals so that the reproduced video signals corrected for time base errors are outputted at a signal output 14. The phase modulating circuit 9 phase modulates the read clock signals Rck in accordance with the velocity error signals to correct the velocity errors of the incoming reproduced video signals. The velocity error signals are supplied to the phase modulating circuit 9 through the aforementioned analog delay circuit 8 adapted to apply, to the aforementioned velocity error signals, a time delay corresponding to the time delay of the video data caused by the time difference between the write and read operations of the video data to and from the memory 13.
In the above described time base correcting apparatus, wherein the incoming video signals are written in the memory by write clock signals Wck modulated by time base errors, and the thus written video signals are read out from the memory by the reference read clock signals Rck modulated by the velocity errors for correcting the time base errors contained in the incoming video signals, the same frequency 910 fh is used for the frequency of the write clock signals Wck and for that of the read clock signals Rck. As a consequence, malfunctions occur due to interference between the two clock signals so that it is difficult with the conventional apparatus to achieve time base compensation of very high accuracy. Especially, in the direct FM recording type video tape recorder, it is necessary to perform time base correction with an extremely high accuracy so that the residual jitter is less than several nanoseconds. Although measures have been adopted to prevent occurrence of the above mentioned malfunction due to the interference of the two clock signals, for example, by providing the data write system and the data read system to and from the memory 13 on separate circuit boards or by providing suitable shields, such measures interfere with the desired reduction in in the costs and the size of the time base correcting apparatus.